14 封装术语
来源：Hitachi Semiconductor Package Data Book. ADE–410–001H, 9th Edition. March (2001)
为了更好的理解相关的封装术语，下面进行了更为详细的罗列：
来自：smta.org：电子封装术语

ASIC Application Specific Integrated Circuit
专用集成电路
BGA Ball Grid Array. A component whose terminations are on the bottom of the package, and are in the shape of solder balls and in a grid array pattern. This generally covers components that have them in a full array or in a partial array with “missing” balls in the center.
球形触点陈列，表面贴装型封装之一。在印刷基板的背面按陈列方式制作出球形凸点用以
代替引脚，在印刷基板的正面装配LSI 芯片，然后用模压树脂或灌封方法进行密封。也称为凸点陈列载体(PAC)。引脚可超过200，是多引脚LSI 用的一种封装。
CBGA/CCGA Ceramic Ball Grid Array/Ceramic Column Grid Array. A grid array packaged component that has ceramic as the substrate of the package, and may have either solder balls or solder columns for connections.
CMOS Complementary Metal Oxide Semiconductor
互补型金属氧化物半导体
COB Chip-on-Board. A situation where the silicon IC chip is mounted directly to the electronic assembly substrate or PWB without an intermediate packaging step. Connections between the chip and the board are generally made with bond wired (also sometime called chip and wire), but the terminology is occasionally used for any chip connection technique such as flip chip (solderable bumps or tape automated bonding.
板上芯片封装，是裸芯片贴装技术之一，半导体芯片交接贴装在印刷线路板上，芯片与基
板的电气连接用引线缝合方法实现，芯片与基板的电气连接用引线缝合方法实现，并用树脂覆盖以确保可靠性。虽然COB 是最简单的裸芯片贴装技术，但它的封装密度远不如TAB 和倒片焊技术。
CSP Chip Scale Package. Active, multi-I/O package that is no larger than 125% of the size of the silicon IC.
芯片级封装
DIL Dual In-Line. Component shape with two parallel rows of connection leads.
DIP 的别称(见DIP)。欧洲半导体厂家多用此名称。
DIP Dual In-Line Package. A popular through hole package with leads in rows on opposite sides of the package.
双列直插式封装。插装型封装之一，引脚从封装两侧引出，封装材料有塑料和陶瓷两种。DIP 是最普及的插装型封装，应用范围包括标准逻辑IC，存贮器LSI，微机电路等。引脚中心距2.54mm，引脚数从6 到64。封装宽度通常为15.2mm。有的把宽度为7.52mm和10.16mm 的封装分别称为skinny DIP 和slim DIP(窄体型DIP)。但多数情况下并不加区分，只简单地统称为DIP。
FCA Flip Chip Attach. The technique of attachment of an IC chip to a substrate using solderable bumps between the silicon chip and substrate.

FPT Fine Pitch Technology. The portion of surface mount technology that included components that typically have lead pitch, or center-to-center spacing, between 0.4mm and 0.8mm.
微间距技术
FP Flat Pack. A low profile IC package, which typically has gull wing type of leads on two or four sides.
扁平封装
FR-4 The most commonly used epoxy-fiberglass material standard for printed circuit boards. The “FR” refers to flame retardant.
由专用电子布浸以环氧酚醛树脂等材料经高温高压热压而成的板状层压制品。
IC Integrated Circuit. A small, complete circuit made by vacuum deposition and other techniques, usually on a silicon chip, and mounted in a package.
集成电路
JEDEC Joint Electronic Devices Engineering Council, a part of the Electronic Industries Association (EIA) that publishes specifications and standards for electronic components.
电子设备工业联合会
LCCC Leadless Ceramic Chip Carrier (or CLCC for Ceramic Leadless Chip Carrier). A hermetically sealed ceramic package that has pads (castellations) around its sides for solder connection in a surface mounting application.
无引线陶瓷芯片载体
LDCC Leaded Ceramic Chip Carrier. A hermetically sealed ceramic package that has leads around its sided for solder connection in a surface mounting application. Typically, thee packages have over 28 leads.
带引脚的陶瓷芯片载体
MCM Multichip Module. A circuit comprised of two or more silicon devices bonded directly to a substrate by wire bond, TAB, of flip chip.
多芯片组件
MELF Metal Electrode Face Bonding. A cylindrical leadless component with a round body and metals terminals on the ends.
金属电极表面接合
PBGA Plastic Ball Grid Array. A ball grid array component whose package substrate is made of plastic, most likely an FR-4 equivalent of epoxy-fiberglass, polyimidearramid, or similar resin-fiber combinations.
塑封球栅阵列型封装
PCB Printed Circuit Board. A part manufactured from a rigid base material upon which a completely processed printed circuit has been formed.
印制电路板
PGA Pad Grid Array. Similar to a pin grid array. An IC package that has solderable connections in a grid layout on the bottom of the package, and is soldered to the surface of the substrate (PWB) with butt solder joints.
陈列引脚封装。插装型封装之一，其底面的垂直引脚呈陈列状排列。封装基材基本上都采用多层陶瓷基板。在未专门表示出材料名称的情况下，多数为陶瓷PGA，用于高速大规模逻辑LSI 电路。成本较高。引脚中心距通常为2.54mm，引脚数从64 到447 左右。为降低成本，封装基材可用玻璃环氧树脂印刷基板代替。也有64～256 引脚的塑料PGA。另外，还有一种引脚中心距为1.27mm 的短引脚表面贴装型PGA(碰焊PGA)。
PLCC Plastic Leaded Chip Carrier. A plastic IC package for surface mounting applications that has leads, generally “J” leads, on all fours sides (sometimes given as PCC or PLDCC).
带引线的塑料芯片载体。表面贴装型封装之一。引脚从封装的四个侧面引出，呈丁字形，是塑料制品。美国德克萨斯仪器公司首先在64k 位DRAM 和256kDRAM 中采用，现在已经普及用于逻辑LSI、DLD(或程逻辑器件)等电路。引脚中心距1.27mm，引脚数从18 到84。J 形引脚不易变形，比QFP 容易操作，但焊接后的外观检查较为困难。
PQFP Plastic Quad Flat Pack. An FP with leads on fours sides. Generally refers to a plastic quad flat package that is built to JEDC standards.
塑料四方扁平封装
QFP Quad Flat Pack. A FP with leads on four sides. Generally refers to a plastic quad flat package that is built to EIJ standards.
四侧引脚扁平封装。表面贴装型封装之一，引脚从四个侧面引出呈海鸥翼(L)型。基材有陶瓷、金属和塑料三种。从数量上看，塑料封装占绝大部分。当没有特别表示出材料时，多数情况为塑料QFP。
QSOP Quarter-Size Small Outline Package. An SO style IC package that has leads on a 25 mil pitch. The name derives from the fact that the package is approximately ½ the length and ½ the width of a standard SOIC, and thus a package of the same pin count occupies approximately ¼ the area on a PWB.
四分之一缩比小外廓封装
SIP Single-In-Line Package. An IC package or multi-component sub-assembly that has connections or leads in a single row on one side.
单列直插式封装
SO Small Outline. A package resembling a flat pack with leads on only two sides.

SOIC Small Outline Integrated Circuit. A plastic IC package for surface mounting applications that has leads on two opposite sides.
小块集成电路
SOJ A plastic IC package with “J” leads on two sides. It resembles a plastic DIP or an SOIC except for lead spacing and forming.
J 形引脚小外型封装。表面贴装型封装之一。引脚从封装两侧引出向下呈J 字形，故此得名。通常为塑料制品，多数用于DRAM 和SRAM 等存储器LSI 电路，但绝大部分是DRAM。用SOJ封装的DRAM 器件很多都装配在SIMM 上。引脚中心距1.27mm，引脚数从20 至40(见SIMM)。
SOL/SOW Small Outline-Large/Small Outline Wide. SO generally refers to a package that  is approximately 150 mils wide, while SOL/SOW refers to packages that are approximately 300 mils wide.

SOP VSOP/SSOP. Another designation for the small outline ICP packages, i.e. Small Outline Package (Very Small Outline Package, Shrink Small Outline Package)
SOP 除了用于存储器LSI 外，也广泛用于规模不太大的ASSP 等电路。在输入输出端子不超过10～40 的领域，SOP 是普及最广的表面贴装封装。引脚中心距1.27mm，引脚数从8～44。另外，引脚中心距小于1.27mm 的SOP 也称为SSOP；装配高度不到1.27mm 的SOP 也称为TSOP(见SSOP、TSOP)。还有一种带有散热片的SOP。
SOT Small Outline Transistor. A plastic leaded package for diodes and transistors used in surface mounting applications.
小外形晶体管
SPC Statistical Process Control. The use of statistical techniques to analyze a process or its output to determine any variation from a benchmark and to take appropriate action to restore statistical control, if required.
统计过程控制
SSOIC Shrink Small Outline IC. An SO style IC package that has leads on a 25 mil pitch.
超小轮廓封装
TBGA Tape Ball Grid Array. A ball grid array component package that uses TAB techniques to make the connections between the IC chip and the solder balls. This results in a solder ball grid array that is only around the periphery, and leaves compliant connections between the IC and the solder balls for better TCE reliability.
载带球栅阵列
VFP Very Fine Pitch. The center-to-center lead distance of surface mount packages that are between 0.012 inch and 0.020 inch.

VSOIC Very Small Outline IC. An SO style IC package that has leads with a pitch of 30 mils or less.

Sources Used:
“Understanding and Using Surface Mount and Fine Pitch Technology”, Charles Hutchins, 1995.
“Surface Mount Technology: Principles and Practice”, Ray Prasad, 1997.
“Surface Mount Technology Terms and Concepts”, Phil Zarrow and Debra Kopp, ITM, 1997.

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