JESD51-11Test Boards for Through-Hole Area Array Leaded

jesd51-11 Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements.pdf

Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements
JESD51-11
JUNE 2001

CONTENTS

1 Scope 1
2 Normative references 1
3 Stock material 2
4 Board outline 3
5 Trace design 3
5.1 Top trace layer layout (both 1s and 2s2p PCBs) 3
5.2 Trace widths for 1s and 2s2p PCBs 4
5.3 Plated through-hole vias 5
5.4 Trace layers and connection routing 5
5.5 Buried layer layout (2s2p PCB only) 6
5.6 PCB metalization characteristics for 1s and 2s2p PCBs 7
5.7 Solder masks for 1s and 2s2p PCBs 7
6 Hand wiring 7
7 Data presentation 8
Tables
1 PCB sizes for packages 3
2 PCB buried plane sizes 6
3 Wire size current limits 7
4 Specified parameters and values used 8
Figures
1a Cross section of 1s PCB showing trace and dielectric thicknesses in package placement 2
and trace fan-out regions
1b Cross section of 2s2p PCB showing trace and dielectric thicknesses 2
2 BGA test board outer dimensions and edge connector design 3
3 Traces to outer ball row flared to perimeter 25 mm from package body 3
4 Flared PCB layout scheme 4
5 Nesting of 256 and 352 PBGA packages 6
6 Routing outside fan-out layer allowed in low conductivity PCB 6
7 Hand wiring test board suggestion 8

1 Scope
This specification covers through-hole area array leaded packages intended to be mounted on a PCB. It does not cover area array packages that require sockets.

早就知道了的!楼主也做LED吗

去 看看怎么样啊  谢谢