JESD51-9 Test Boards for Area Array Surface Mount Package

jesd51-9 Test Boards for Area Array Surface Mount Package Thermal Measurements.pdf

Test Boards for Area Array Surface Mount Package Thermal Measurements
JESD51-9
JULY 2000

CONTENTS
Page
Foreword i
1 Scope 1
2 Normative references 1
3 Stock material 2
4 Board outline 3
5 Trace design 3
5.1 Top trace layer layout (both 1s and 2s2p PCBs) 3
5.2 Traces to thermal balls 4
5.3 Trace widths for 1s and 2s2p PCBs 4
5.4 Ball lands for 1s and 2s2p PCBs 5
5.5 Thermal ball lands and thermal vias 5
5.6 Trace layers and connection routing 6
5.7 Buried layer layout (2s2p PCB only) 7
5.8 PCB metalization characteristics for 1s and 2s2p PCBs 7
5.9 Solder masks for 1s and 2s2p PCBs 7
5.10 Plated through-hole vias for 1s and 2s2p PCBs 8
6 Hand wiring 8
7 Data presentation 9
Tables
1 PCB sizes for packages 3
2 Drill diameters for thermal vias vs. ball pitch 6
3 PCB buried plane sizes 7
4 Wire size current limits 8
5 Specified parameters and values used 9
Figures
1a Cross section of 1s PCB showing trace and dielectric thicknesses in package placement 2
and trace fan-out regions
1b Cross section of 2s2p PCB showing trace and dielectric thicknesses 2
2 BGA test board outer dimensions and edge connector design 3
3 Traces to outer ball row flared to perimeter 25 mm from package body 3
4 Flared PCB layout scheme 5
5 Package footprint routing 5
6 Nesting of 256 and 352 PBGA packages 7
7 Routing outside fan-out layer allowed in low conductivity PCB 7
8 Hand wiring test board suggestion 9